Joel Emer's research encompasses processor micro-architectures, processor performance modeling, and evaluation techniques
Joel Emer is a professor of the practice in the Department of Electrical Engineering and Computer Science, and a member of the Computer Science & Artificial Intelligence Lab at MIT. Emer has held various research and advanced development positions investigating processor micro-architecture and developing performance modeling and evaluation techniques. He has made architectural contributions to a number of VAX, Alpha and X86 processors and is recognized as one of the developers of the widely employed quantitative approach to processor performance evaluation. He has also been recognized for his contributions in the advancement of simultaneous multi-threading technology, analysis of the architectural impact of soft errors, memory dependence prediction, pipeline and cache organization, performance modeling methodologies and spatial architectures. Emer received his PhD in electrical engineering from the University of Illinois, and MA and BS in electrical engineering from Purdue University. Emer is a fellow of both the ACM and the IEEE, and a member of the National Academy of Engineering. He received the Eckert-Mauchly award for lifetime contributions in computer architecture.